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authorBas Nieuwenhuizen <[email protected]>2018-07-14 14:28:21 +0200
committerBas Nieuwenhuizen <[email protected]>2018-07-19 02:38:01 +0200
commit82664af6cf12b1ab7436bdcb3792315c433322d7 (patch)
tree4abb12b1866431a79b70f3ff049a62f4c6c987a2 /src/amd
parent760211b77c7aabc9264542f18e42f366b0fef33f (diff)
radv: Select correct entries for binning.
Overshot it by one every time. CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_pipeline.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4c794d9515d..27e13a2251c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2468,7 +2468,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
}
const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
- while(color_entry->bpp <= color_bytes_per_pixel)
+ while(color_entry[1].bpp <= color_bytes_per_pixel)
++color_entry;
extent = color_entry->extent;
@@ -2482,7 +2482,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
- while(ds_entry->bpp <= ds_bytes_per_pixel)
+ while(ds_entry[1].bpp <= ds_bytes_per_pixel)
++ds_entry;
extent.width = MIN2(extent.width, ds_entry->extent.width);