summaryrefslogtreecommitdiffstats
path: root/src/amd
diff options
context:
space:
mode:
authorBas Nieuwenhuizen <[email protected]>2018-01-04 02:11:51 +0100
committerBas Nieuwenhuizen <[email protected]>2018-01-04 19:35:36 +0100
commit76daa30e4a0d3dfe04c5b79fcdfba17fb1656ccd (patch)
treef78635ef076cf4db6530389e5da75ef55591a048 /src/amd
parentf2c9f13ec2fdab99f5aa7f32845ee94dd1942fe9 (diff)
radv: Use correct flush bits for flushing L2 during CB/DB flushes.
Copied from radeonsi. Putting in the correct metadata flush commands for eventually not flushing L2 on CB/DB switch. Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT at the moment. Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/si_cmd_buffer.c29
1 files changed, 16 insertions, 13 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 7d75d69a9a8..e16765b5aec 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1006,24 +1006,27 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
#else
cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
#endif
- /* TC | TC_WB = invalidate L2 data
- * TC_MD | TC_WB = invalidate L2 metadata
- * TC | TC_WB | TC_MD = invalidate L2 data & metadata
+ /* These are the only allowed combinations. If you need to
+ * do multiple operations at once, do them separately.
+ * All operations that invalidate L2 also seem to invalidate
+ * metadata. Volatile (VOL) and WC flushes are not listed here.
*
- * The metadata cache must always be invalidated for coherency
- * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
- *
- * TC must be invalidated on GFX9 only if the CB/DB surface is
- * not pipe-aligned. If the surface is RB-aligned, it might not
- * strictly be pipe-aligned since RB alignment takes precendence.
+ * TC | TC_WB = writeback & invalidate L2 & L1
+ * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
+ * TC_WB | TC_NC = writeback L2 for MTYPE == NC
+ * TC | TC_NC = invalidate L2 for MTYPE == NC
+ * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
+ * TCL1 = invalidate L1
*/
- tc_flags = EVENT_TC_WB_ACTION_ENA |
- EVENT_TC_MD_ACTION_ENA;
+ tc_flags = EVENT_TC_ACTION_ENA |
+ EVENT_TC_MD_ACTION_ENA;
/* Ideally flush TC together with CB/DB. */
if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
- tc_flags |= EVENT_TC_ACTION_ENA |
- EVENT_TCL1_ACTION_ENA;
+ /* Writeback and invalidate everything in L2 & L1. */
+ tc_flags = EVENT_TC_ACTION_ENA |
+ EVENT_TC_WB_ACTION_ENA;
+
/* Clear the flags. */
flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |