diff options
| author | Samuel Pitoiset <[email protected]> | 2019-11-06 16:31:56 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-12-10 13:09:26 +0100 |
| commit | 41cebfc9c1e304f86e70a4fb57f4d8d28eb3c720 (patch) | |
| tree | cf3838d3ed8332e98f09cc33e997768d0cd600d5 /src/amd | |
| parent | b603cc8c841c0c3ebec236a648e731caeb0a9b8d (diff) | |
radv: do not init HTILE as compressed state when dst layout allows it
I don't think this makes much differences and a potential clear
following the initialization will overwrite HTILE anyways.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c866528d368..bbbb190394c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5126,19 +5126,19 @@ void radv_CmdEndRenderPass2KHR( */ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - const VkImageSubresourceRange *range, - uint32_t clear_word) + const VkImageSubresourceRange *range) { assert(range->baseMipLevel == 0); assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS); VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT; struct radv_cmd_state *state = &cmd_buffer->state; + uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f; VkClearDepthStencilValue value = {}; state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; - state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word); + state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value); state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; @@ -5172,18 +5172,10 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe return; if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f; - - if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, - dst_queue_mask)) { - clear_value = 0; - } - - radv_initialize_htile(cmd_buffer, image, range, clear_value); + radv_initialize_htile(cmd_buffer, image, range); } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { - uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f; - radv_initialize_htile(cmd_buffer, image, range, clear_value); + radv_initialize_htile(cmd_buffer, image, range); } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) && !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | |