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authorSamuel Pitoiset <[email protected]>2019-08-20 17:20:42 +0200
committerSamuel Pitoiset <[email protected]>2019-08-27 08:04:29 +0200
commit2b9c371575a83437f4150ee83843fab3271d3978 (patch)
treef43fe89f7af6aa23a83a32e58341ff6f86867029 /src/amd
parentb027ad66d729e31430d63406e70ac52d373e8fec (diff)
ac: add cpdma_prefetch_writes_memory to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/common/ac_gpu_info.c2
-rw-r--r--src/amd/common/ac_gpu_info.h1
-rw-r--r--src/amd/vulkan/radv_device.c2
-rw-r--r--src/amd/vulkan/radv_private.h1
-rw-r--r--src/amd/vulkan/radv_shader.c2
5 files changed, 4 insertions, 4 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6c91a5bd848..b56460f8b32 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -465,6 +465,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
(info->chip_class >= GFX8 &&
info->me_fw_feature >= 41);
+ info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index ea6b9111108..a1d4d142493 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -64,6 +64,7 @@ struct radeon_info {
bool has_rbplus; /* if RB+ registers exist */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
+ bool cpdma_prefetch_writes_memory;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5406ec72239..9786b4704ee 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -363,8 +363,6 @@ radv_physical_device_init(struct radv_physical_device *device,
device->rad_info.family == CHIP_RENOIR;
}
- device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
-
/* Vega10/Raven need a special workaround for a hardware bug. */
device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
device->rad_info.family == CHIP_RAVEN;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 380e2a8e632..abbfa8d8c3f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -281,7 +281,6 @@ struct radv_physical_device {
struct wsi_device wsi_device;
bool rbplus_allowed; /* if RB+ is allowed */
- bool cpdma_prefetch_writes_memory;
bool has_scissor_bug;
bool has_tc_compat_zrange_bug;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f7ef20e89b0..c0e122a6ba7 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -631,7 +631,7 @@ radv_alloc_shader_memory(struct radv_device *device,
slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
RADEON_DOMAIN_VRAM,
RADEON_FLAG_NO_INTERPROCESS_SHARING |
- (device->physical_device->cpdma_prefetch_writes_memory ?
+ (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
0 : RADEON_FLAG_READ_ONLY),
RADV_BO_PRIORITY_SHADER);
slab->ptr = (char*)device->ws->buffer_map(slab->bo);