diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-04-22 18:42:20 +0200 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-04-22 20:26:59 +0100 |
| commit | e137b9eed9501858e2037719a94aafee35179249 (patch) | |
| tree | 9ec53e40b115be4cf29b5de797e7b41df0e6c5eb /src/amd | |
| parent | 9da0cd56c3f95081bd4cc7efe87d2b475019b17d (diff) | |
radv: Use the correct pipeline for dispatches.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Fixes: ec15e0d30 "radv: optimise compute shader grid size emission."
Tested-by: Grazvydas Ignotas <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 40e6e432ae7..de103855158 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2843,7 +2843,7 @@ void radv_CmdDispatch( MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { assert(!loc->indirect); - uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; assert(loc->num_sgprs == grid_used); radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used); radeon_emit(cmd_buffer->cs, x); @@ -2882,7 +2882,7 @@ void radv_CmdDispatchIndirect( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { - uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; for (unsigned i = 0; i < grid_used; ++i) { radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | @@ -2954,7 +2954,7 @@ void radv_unaligned_dispatch( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { - uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used); radeon_emit(cmd_buffer->cs, blocks[0]); if (grid_used > 1) |