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authorConnor Abbott <[email protected]>2019-06-05 16:54:24 +0200
committerConnor Abbott <[email protected]>2019-06-06 17:14:28 +0200
commit9d93d2a4049c0635e75c8eff85c8be7603599340 (patch)
tree01a0cb9e5ebd1100a23696c5d9e6d2f9e8b87ac8 /src/amd
parent1d55b0da59dd4b863df7c35f697409e80b1ffd50 (diff)
ac/nir: Remove stale TODO
While we're here, copy the comment explaining this from radeonsi. Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/common/ac_nir_to_llvm.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index dd673cf5ea0..360e139bf5f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3895,7 +3895,13 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
args.offset = NULL;
}
- /* TODO TG4 support */
+ /* DMASK was repurposed for GATHER4. 4 components are always
+ * returned and DMASK works like a swizzle - it selects
+ * the component to fetch. The only valid DMASK values are
+ * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
+ * (red,red,red,red) etc.) The ISA document doesn't mention
+ * this.
+ */
args.dmask = 0xf;
if (instr->op == nir_texop_tg4) {
if (instr->is_shadow)