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authorMarek Olšák <[email protected]>2017-10-09 18:42:48 +0200
committerMarek Olšák <[email protected]>2017-10-12 19:03:33 +0200
commit5f2073be3282a233a8b5bcb5342ea5e599b9b316 (patch)
treef80d4a27f109ea95e889cfbbf62b7b6d8bde6908 /src/amd
parentc3f3685fd655550bb189aac814126e5feb56db2b (diff)
ac/surface: add ac_surface::is_displayable
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/common/ac_surface.c11
-rw-r--r--src/amd/common/ac_surface.h2
2 files changed, 13 insertions, 0 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 22c653f0c4f..f956c14a106 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -795,6 +795,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->htile_size *= 2;
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
+ surf->is_displayable = surf->is_linear ||
+ surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
+ surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
return 0;
}
@@ -1156,6 +1159,14 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
+ /* Query whether the surface is displayable. */
+ bool displayable = false;
+ r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
+ surf->bpe * 8, &displayable);
+ if (r)
+ return r;
+ surf->is_displayable = displayable;
+
switch (surf->u.gfx9.surf.swizzle_mode) {
/* S = standard. */
case ADDR_SW_256B_S:
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 96138b968ab..7ac4737e6df 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -161,6 +161,8 @@ struct radeon_surf {
unsigned num_dcc_levels:4;
unsigned is_linear:1;
unsigned has_stencil:1;
+ /* This might be true even if micro_tile_mode isn't displayable or rotated. */
+ unsigned is_displayable:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3;
uint32_t flags;