diff options
author | Marek Olšák <[email protected]> | 2018-05-02 18:39:04 -0400 |
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committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:54 -0400 |
commit | 09f1bab483cc8011a6299e2aca805b6ad06aab82 (patch) | |
tree | ae424cb9f01a649e49c04bc491568e3aa60928bb /src/amd | |
parent | 8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882 (diff) |
ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 | ||||
-rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index e2e41f0f47a..6f2fea895be 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -318,6 +318,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, !info->has_dedicated_vram; info->kernel_flushes_hdp_before_ib = true; info->htile_cmask_support_1d_tiling = true; + info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -467,6 +468,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_local_buffers = %u\n", info->has_local_buffers); printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib); printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling); + printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 578c3fb7da1..bc6350b5625 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -98,6 +98,7 @@ struct radeon_info { bool has_local_buffers; bool kernel_flushes_hdp_before_ib; bool htile_cmask_support_1d_tiling; + bool si_TA_CS_BC_BASE_ADDR_allowed; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ |