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authorBas Nieuwenhuizen <[email protected]>2017-10-20 01:08:30 +0200
committerDave Airlie <[email protected]>2017-10-20 06:14:14 +0100
commitf82797b56d9646798c3f02eca2878b6702cbe700 (patch)
treeaf8dcc0eaab3b9aadd4ae3ba34d2a11177d2c55e /src/amd
parent6e21b7a2947dc0dd7e8265395a43af516a0622cf (diff)
radv: Only emit TES when it exists.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a62aa6ccb9c..3dc356ca8e0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -768,10 +768,12 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
- if (tes->info.tes.as_es)
- radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
- else
- radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
+ if (tes) {
+ if (tes->info.tes.as_es)
+ radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
+ else
+ radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
+ }
radv_emit_hw_hs(cmd_buffer, tcs);