diff options
author | Timur Kristóf <[email protected]> | 2019-11-22 15:13:54 +0100 |
---|---|---|
committer | Daniel Schürmann <[email protected]> | 2019-12-04 10:36:01 +0000 |
commit | dd9dad731bed71a77f28111b2d548b9d5163cd64 (patch) | |
tree | 406e13efb7303a1e44a3583722176fd73cacd17c /src/amd | |
parent | 753670e9028cdb067405f7f27e29012db719732f (diff) |
aco: Optimize load_subgroup_id to one bit field extract instruction.
Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Rhys Perry <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 505dd101355..f262d0f7e5a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5654,9 +5654,8 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) } case nir_intrinsic_load_subgroup_id: { if (ctx->stage == compute_cs) { - Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u), - get_arg(ctx, ctx->args->ac.tg_size)); - bld.sop2(aco_opcode::s_lshr_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), tg_num, Operand(0x6u)); + bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), + get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16))); } else { bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u)); } |