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authorSamuel Pitoiset <[email protected]>2020-03-17 15:32:45 +0100
committerMarge Bot <[email protected]>2020-03-18 11:36:24 +0000
commit94e37859a96cc56cf0c5418a5af00a3e9f5a1bf5 (patch)
treec0017c9a0e7f8d4a7c49aa5507d643bdd92aaefd /src/amd
parenta6625b15a466e2648a35810c64df882ea869971c (diff)
radv: fix random depth range unrestricted failures due to a cache issue
The shader module name is used to compute the pipeline key. The driver used to load the wrong pipelines because the shader names were similar. This should fix random failures of dEQP-VK.pipeline.depth_range_unrestricted.* Fixes: f11ea226664 ("radv: fix a performance regression with graphics depth/stencil clears") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_meta_clear.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 5ca510dfd62..62c17af7fe9 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -512,8 +512,12 @@ build_depthstencil_shader(struct nir_shader **out_vs,
nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
- vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
- fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
+ vs_b.shader->info.name = ralloc_strdup(vs_b.shader,
+ unrestricted ? "meta_clear_depthstencil_unrestricted_vs"
+ : "meta_clear_depthstencil_vs");
+ fs_b.shader->info.name = ralloc_strdup(fs_b.shader,
+ unrestricted ? "meta_clear_depthstencil_unrestricted_fs"
+ : "meta_clear_depthstencil_fs");
const struct glsl_type *position_out_type = glsl_vec4_type();
nir_variable *vs_out_pos =