diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-09 08:27:29 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-09 09:54:12 +0200 |
| commit | 2974df819e40563916242eae7acddc0200fd69a0 (patch) | |
| tree | a7e710a75bcb0d5f1e365b8b244b782f9f289770 /src/amd | |
| parent | 53c75f17ece9a20d93fbd53b1043ebcd8ee36349 (diff) | |
radv: set max workgroup size to 128 for TES as NGG on GFX10
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 9644185f870..67630c4ee92 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3721,7 +3721,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, } if (ctx.ac.chip_class >= GFX10) { - if (shaders[0]->info.stage == MESA_SHADER_VERTEX && + if (is_pre_gs_stage(shaders[0]->info.stage) && options->key.vs.out.as_ngg) { ctx.max_workgroup_size = 128; } |