diff options
| author | Dave Airlie <[email protected]> | 2018-03-14 10:21:46 +1000 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2018-03-20 16:57:26 +0000 |
| commit | 876880b7524092d19cfcc353302d0db89f4d219d (patch) | |
| tree | ea19a3138c06b3ba48d9786833ffb2a545d95491 /src/amd | |
| parent | 14f55a8221b4b714737ee95c80c39bf33837a039 (diff) | |
radv: mark all tess output for an indirect access.
If a shader does a tcs store with an indirect access, we
were only marking the first spot as used. For indirect access
we always now mark all slots used by the variable.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.)
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit 27a5e5366e89498d98d786cc84fafbdb220c4d94)
Emil Velikov: move hunks {radv,ac}_nir_to_llvm.c]
Signed-off-by: Emil Velikov <[email protected]>
Conflicts:
src/amd/vulkan/radv_nir_to_llvm.c
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 5588a723720..33b62033ab8 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2846,13 +2846,14 @@ static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context static void mark_tess_output(struct nir_to_llvm_context *ctx, - bool is_patch, uint32_t param) + bool is_patch, uint32_t param, int num_slots) { + uint64_t slot_mask = (1ull << num_slots) - 1; if (is_patch) { - ctx->tess_patch_outputs_written |= (1ull << param); + ctx->tess_patch_outputs_written |= (slot_mask << param); } else - ctx->tess_outputs_written |= (1ull << param); + ctx->tess_outputs_written |= (slot_mask<< param); } static LLVMValueRef @@ -2948,6 +2949,7 @@ store_tcs_output(struct ac_shader_abi *abi, const unsigned component = var->data.location_frac; const bool is_patch = var->data.patch; const bool is_compact = var->data.compact; + const unsigned count = glsl_count_attribute_slots(var->type, false); LLVMValueRef dw_addr; LLVMValueRef stride = NULL; LLVMValueRef buf_addr = NULL; @@ -2976,7 +2978,10 @@ store_tcs_output(struct ac_shader_abi *abi, dw_addr = get_tcs_out_current_patch_data_offset(ctx); } - mark_tess_output(ctx, is_patch, param); + if (param_index) + mark_tess_output(ctx, is_patch, param, count); + else + mark_tess_output(ctx, is_patch, param, 1); dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride, param_index); @@ -6223,9 +6228,9 @@ handle_ls_outputs_post(struct nir_to_llvm_context *ctx) if (i == VARYING_SLOT_CLIP_DIST0) length = ctx->num_output_clips + ctx->num_output_culls; int param = shader_io_get_unique_index(i); - mark_tess_output(ctx, false, param); + mark_tess_output(ctx, false, param, 1); if (length > 4) - mark_tess_output(ctx, false, param + 1); + mark_tess_output(ctx, false, param + 1, 1); LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr, LLVMConstInt(ctx->ac.i32, param * 4, false), ""); @@ -6368,8 +6373,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx) tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER); tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER); - mark_tess_output(ctx, true, tess_inner_index); - mark_tess_output(ctx, true, tess_outer_index); + mark_tess_output(ctx, true, tess_inner_index, 1); + mark_tess_output(ctx, true, tess_outer_index, 1); lds_base = get_tcs_out_current_patch_data_offset(ctx); lds_inner = LLVMBuildAdd(ctx->builder, lds_base, LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), ""); |