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authorDave Airlie <[email protected]>2017-07-09 20:34:04 +0100
committerDave Airlie <[email protected]>2017-07-09 22:17:59 +0100
commitedf2acbeb16112fe002d3f7208018273d413f25c (patch)
tree4e10163f3c5b54e5242851b608dff1400a3aa9e5 /src/amd
parentf3958f1644391ed5f6d14373ac74d4978d8598b7 (diff)
radv: add support for using addrlib max alignment.
Rather than using 64k, use what addrlib returns as the base alignment for vulkan allocations. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/common/ac_gpu_info.h1
-rw-r--r--src/amd/common/ac_surface.c10
-rw-r--r--src/amd/common/ac_surface.h3
-rw-r--r--src/amd/vulkan/radv_device.c2
-rw-r--r--src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c2
5 files changed, 14 insertions, 4 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 3091fed6a43..72a85062466 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -95,6 +95,7 @@ struct radeon_info {
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
+ uint64_t max_alignment; /* from addrlib */
/* Tile modes. */
uint32_t si_tile_mode_array[32];
uint32_t cik_macrotile_mode_array[16];
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 877d592ab81..a4df595653b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -150,12 +150,14 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInpu
}
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
- const struct amdgpu_gpu_info *amdinfo)
+ const struct amdgpu_gpu_info *amdinfo,
+ uint64_t *max_alignment)
{
ADDR_CREATE_INPUT addrCreateInput = {0};
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
+ ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
@@ -202,6 +204,12 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
if (addrRet != ADDR_OK)
return NULL;
+ if (max_alignment) {
+ addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
+ if (addrRet == ADDR_OK){
+ *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
+ }
+ }
return addrCreateOutput.hLib;
}
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 582a67193f8..4d893ff5009 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -206,7 +206,8 @@ struct ac_surf_config {
};
ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
- const struct amdgpu_gpu_info *amdinfo);
+ const struct amdgpu_gpu_info *amdinfo,
+ uint64_t *max_alignment);
int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
const struct ac_surf_config * config,
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d1c519a1b7a..c31a687cbd2 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2134,7 +2134,7 @@ VkResult radv_AllocateMemory(
if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
flags |= RADEON_FLAG_GTT_WC;
- mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
+ mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
domain, flags);
if (!mem->bo) {
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index c7688cf4c9b..25034895883 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -53,7 +53,7 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
return false;
}
- ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo);
+ ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
return false;