diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-31 09:39:20 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-31 12:14:29 +0200 |
| commit | e041a74588b2976a975851b3a6096dbe89864026 (patch) | |
| tree | ff037fd7b9876adedbbffd945ff18582f363b444 /src/amd | |
| parent | 0e1724af61d79a241026f2714dc23723f0e3d286 (diff) | |
radv/gfx10: implement a bug workaround for GE_PC_ALLOC
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 17 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 13 |
2 files changed, 13 insertions, 17 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5c913f29a5a..4d4f86a7e24 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3457,18 +3457,6 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, } static void -gfx10_set_ge_pc_alloc(struct radeon_cmdbuf *ctx_cs, - struct radv_pipeline *pipeline, - bool culling) -{ - struct radeon_info *info = &pipeline->device->physical_device->rad_info; - - radeon_set_uconfig_reg(ctx_cs, R_030980_GE_PC_ALLOC, - S_030980_OVERSUB_EN(1) | - S_030980_NUM_PC_LINES((culling ? 256 : 128) * info->max_se - 1)); -} - -static void radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, @@ -3534,9 +3522,6 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index); - - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) - gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false); } static void @@ -3699,8 +3684,6 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) | S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); - - gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false); } static void diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 18b2236e54b..3d6c672dd0f 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -382,6 +382,19 @@ si_emit_graphics(struct radv_physical_device *physical_device, S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1)); radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); + + if (physical_device->rad_info.family == CHIP_NAVI10 || + physical_device->rad_info.family == CHIP_NAVI12 || + physical_device->rad_info.family == CHIP_NAVI14) { + /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */ + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); + } + + /* TODO: For culling, replace 128 with 256. */ + radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, + S_030980_OVERSUB_EN(1) | + S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1)); } if (physical_device->rad_info.chip_class >= GFX8) { |