diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-24 17:03:28 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-06-25 16:36:23 +0200 |
| commit | a5ba386b3ff349f3fd13379804b260f33c58d983 (patch) | |
| tree | f1ace1d25c72875f0db3d97c2aff9395b5cd5f6a /src/amd | |
| parent | 1931c97a1dc71f8fb548a23247c2a0dd4793ad3c (diff) | |
radv: always initialize levels without DCC as fully expanded
This fixes a rendering issue with RoTR/DXVK.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 215ccced144..db855dfc76c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4960,26 +4960,24 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer, * support fast clears and we have to initialize them as "fully * expanded". */ - if (image->planes[0].surface.num_dcc_levels > 1) { - /* Compute the size of all fast clearable DCC levels. */ - for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) { - struct legacy_surf_level *surf_level = - &image->planes[0].surface.u.legacy.level[i]; + /* Compute the size of all fast clearable DCC levels. */ + for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) { + struct legacy_surf_level *surf_level = + &image->planes[0].surface.u.legacy.level[i]; - if (!surf_level->dcc_fast_clear_size) - break; + if (!surf_level->dcc_fast_clear_size) + break; - size = surf_level->dcc_offset + surf_level->dcc_fast_clear_size; - } + size = surf_level->dcc_offset + surf_level->dcc_fast_clear_size; + } - /* Initialize the mipmap levels without DCC. */ - if (size != image->planes[0].surface.dcc_size) { - state->flush_bits |= - radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->dcc_offset + size, - image->planes[0].surface.dcc_size - size, - 0xffffffff); - } + /* Initialize the mipmap levels without DCC. */ + if (size != image->planes[0].surface.dcc_size) { + state->flush_bits |= + radv_fill_buffer(cmd_buffer, image->bo, + image->offset + image->dcc_offset + size, + image->planes[0].surface.dcc_size - size, + 0xffffffff); } } |