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authorSamuel Pitoiset <[email protected]>2020-01-29 14:38:55 +0100
committerDylan Baker <[email protected]>2020-04-09 14:16:23 -0700
commita0e857c7682e134034a7f416120c4deeed6754d7 (patch)
treedec11f7ae887344ccfd1ebfd3780b3ecb10a9719 /src/amd
parent87f1e7b1d8c413d49c6a8281d63f9466fd1308f6 (diff)
ac/nir: split 8-bit SSBO stores on GFX6
Due to possible alignment issues, make sure to split stores of 8-bit vectors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339> (cherry picked from commit c6bf1597d1e8abf122371118b04a85ee0aa6b3d5)
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/llvm/ac_nir_to_llvm.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 577a1b6cd75..6acef5e7fb7 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1734,6 +1734,15 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
count = 1;
num_bytes = 2;
}
+
+ /* Due to alignment issues, split stores of 8-bit vectors. */
+ if (ctx->ac.chip_class == GFX6 &&
+ elem_size_bytes == 1 && count > 1) {
+ writemask |= ((1u << (count - 1)) - 1u) << (start + 1);
+ count = 1;
+ num_bytes = 1;
+ }
+
data = extract_vector_range(&ctx->ac, base_data, start, count);
offset = LLVMBuildAdd(ctx->ac.builder, base_offset,