diff options
author | Marek Olšák <[email protected]> | 2019-09-24 16:56:21 -0400 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2019-09-30 13:36:20 -0400 |
commit | 8cbe83445b2ec78fab1f303918c79268713500b5 (patch) | |
tree | efa92b1d6671b2f68e79bfba176e3cc5cbbdbcf1 /src/amd | |
parent | 7d97013294816db46abb7d1e7c6871fe73dfac93 (diff) |
ac: add radeon_info::tcc_harvested
Cc: 19.2 <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r-- | src/amd/common/ac_gpu_info.c | 4 | ||||
-rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 41713b5348e..b5e0b8415d2 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -470,6 +470,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, } if (info->chip_class >= GFX10) { info->tcc_cache_line_size = 128; + /* This is a hack, but it's all we can do without a kernel upgrade. */ + info->tcc_harvested = + (info->vram_size / info->num_tcc_blocks) != 512*1024*1024; } else { info->tcc_cache_line_size = 64; } @@ -694,6 +697,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" num_sdma_rings = %i\n", info->num_sdma_rings); printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq); printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size); + printf(" tcc_harvested = %u\n", info->tcc_harvested); printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned); printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index a21bd51e29d..a2adab88ec4 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -58,6 +58,7 @@ struct radeon_info { uint32_t num_sdma_rings; uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + bool tcc_harvested; bool has_clear_state; bool has_distributed_tess; bool has_dcc_constant_encode; |