diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-09 08:27:31 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-09 09:54:16 +0200 |
| commit | 54e2470047d2c86718f3187be7aa3b651270cd36 (patch) | |
| tree | 34896cf90771a3d38eabad2e86e1eaddb161cdd2 /src/amd | |
| parent | d2a8b63a2c3963d670887ae442671b01b306632d (diff) | |
radv: fix setting VGT_REUSE_OFF for TES on GFX10
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 91ce108ef92..d2002dd904b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3338,6 +3338,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, const struct radv_ngg_state *ngg_state) { uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; + gl_shader_stage es_type = + radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_emit(cs, va >> 8); @@ -3388,9 +3390,12 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, cull_dist_mask << 8 | clip_dist_mask); - /* TODO: Correctly set REUSE_OFF */ + bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 && + pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 && + es_type == MESA_SHADER_TESS_EVAL; + radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, - S_028AB4_REUSE_OFF(0)); + S_028AB4_REUSE_OFF(vgt_reuse_off)); radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, ngg_state->vgt_esgs_ring_itemsize); |