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authorDave Airlie <[email protected]>2017-06-01 05:32:25 +0100
committerDave Airlie <[email protected]>2017-06-02 12:49:01 +1000
commit745aa17093abe179b2366087ceb823d53cd6dfbf (patch)
tree6c38ac9e9554f86c2c3b1eb30636c0dc3e9cfcc0 /src/amd
parentad61eac250120eec44a305e6872a63c21ec683cc (diff)
radv: bump some base addresses to 64-bits.
For GFX9 these will be needed to be 64-bit, so bump them early, to avoid it causing any wierdness later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_private.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 16f95c40ef1..f3a3b3c6ba5 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1335,36 +1335,36 @@ struct radv_sampler {
};
struct radv_color_buffer_info {
- uint32_t cb_color_base;
+ uint64_t cb_color_base;
+ uint64_t cb_color_cmask;
+ uint64_t cb_color_fmask;
+ uint64_t cb_dcc_base;
uint32_t cb_color_pitch;
uint32_t cb_color_slice;
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
uint32_t cb_dcc_control;
- uint32_t cb_color_cmask;
uint32_t cb_color_cmask_slice;
- uint32_t cb_color_fmask;
uint32_t cb_color_fmask_slice;
uint32_t cb_clear_value0;
uint32_t cb_clear_value1;
- uint32_t cb_dcc_base;
uint32_t micro_tile_mode;
};
struct radv_ds_buffer_info {
+ uint64_t db_z_read_base;
+ uint64_t db_stencil_read_base;
+ uint64_t db_z_write_base;
+ uint64_t db_stencil_write_base;
+ uint64_t db_htile_data_base;
uint32_t db_depth_info;
uint32_t db_z_info;
uint32_t db_stencil_info;
- uint32_t db_z_read_base;
- uint32_t db_stencil_read_base;
- uint32_t db_z_write_base;
- uint32_t db_stencil_write_base;
uint32_t db_depth_view;
uint32_t db_depth_size;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
- uint32_t db_htile_data_base;
uint32_t pa_su_poly_offset_db_fmt_cntl;
float offset_scale;
};