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| author | Matt Turner <[email protected]> | 2017-08-29 18:29:29 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2017-10-04 14:08:54 -0700 |
| commit | 2572c2771d0cab0b9bc489d354ede44dfc88547b (patch) | |
| tree | 816858b13a832a1a8a16f420c39f318154550c33 /src/amd | |
| parent | 98298c7e3da3a8368d618199d8a50e638c257779 (diff) | |
i965: Validate "Special Requirements for Handling Double Precision Data Types"
I did not implement:
CNL's restriction on 64-bit int + align16, because I don't think
we'll ever use this combination regardless of hardware generation.
The restriction on immediate DF -> F conversions, because there's no
reason to ever generate that, and I don't even know how DF -> F
conversions are supposed to work in Align16 since (1) the dst stride
must be 1, but (2) the dst stride would have to be 2 for src and dst
strides to be aligned.
Diffstat (limited to 'src/amd')
0 files changed, 0 insertions, 0 deletions