diff options
| author | Dave Airlie <[email protected]> | 2017-04-13 14:36:26 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-04-13 20:32:03 +1000 |
| commit | 01d0c5a92294e3413a8e72970e25635057674659 (patch) | |
| tree | aac913d82ec0a8e7ee617ca05f345aca0b275709 /src/amd | |
| parent | 4bcebe10ca322c1237d93a0bb786b91731f90589 (diff) | |
radv: fix stencil regression since new addrlib import
The addrlib import meant we'd return after we attempted
to setup the no stencil bits for an S8_UINT, now we break
and use the stencil level info when creating stencil DB
info.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 8 | ||||
| -rw-r--r-- | src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 2 |
2 files changed, 9 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 5f14394196a..b099ec736c0 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2732,6 +2732,7 @@ radv_initialise_ds_surface(struct radv_device *device, unsigned format; uint64_t va, s_offs, z_offs; const struct radeon_surf_level *level_info = &iview->image->surface.level[level]; + bool stencil_only = false; memset(ds, 0, sizeof(*ds)); switch (iview->vk_format) { case VK_FORMAT_D24_UNORM_S8_UINT: @@ -2750,6 +2751,10 @@ radv_initialise_ds_surface(struct radv_device *device, S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); ds->offset_scale = 1.0f; break; + case VK_FORMAT_S8_UINT: + stencil_only = true; + level_info = &iview->image->surface.stencil_level[level]; + break; default: break; } @@ -2784,6 +2789,9 @@ radv_initialise_ds_surface(struct radv_device *device, unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; + if (stencil_only) + tile_mode = stencil_tile_mode; + ds->db_depth_info |= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) | S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) | diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c index 0433952e749..511f464df6a 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c @@ -486,7 +486,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, r = radv_compute_level(ws->addrlib, surf, false, level, type, compressed, &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut); if (r) - return r; + break; if (level == 0) { surf->bo_alignment = AddrSurfInfoOut.baseAlign; |