diff options
| author | Samuel Pitoiset <[email protected]> | 2017-10-06 15:39:00 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-10-09 10:05:04 +0200 |
| commit | 5848565ee31a10bfe8d941d6f5599a55eb7d8979 (patch) | |
| tree | cf469ff1b1a63d80e5636a3b3a6048d10ce392b9 /src/amd | |
| parent | aab1537568475fefcf2981c87a7b1689f655a4e7 (diff) | |
radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()
These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 16 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 15 |
2 files changed, 15 insertions, 16 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3f6945bfea3..a9e0fa51767 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -488,13 +488,6 @@ radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2); } -/* 12.4 fixed-point */ -static unsigned radv_pack_float_12p4(float x) -{ - return x <= 0 ? 0 : - x >= 4096 ? 0xffff : x * 16; -} - struct ac_userdata_info * radv_lookup_user_sgpr(struct radv_pipeline *pipeline, gl_shader_stage stage, @@ -588,19 +581,10 @@ radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL, raster->pa_cl_clip_cntl); - radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0, raster->spi_interp_control); - - radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2); - unsigned tmp = (unsigned)(1.0 * 8.0); - radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); - radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | - S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */ - radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL, raster->pa_su_vtx_cntl); - radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL, raster->pa_su_sc_mode_cntl); } diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index f0b3db76416..b8eb9b4c7e1 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -216,6 +216,13 @@ si_init_compute(struct radv_cmd_buffer *cmd_buffer) si_emit_compute(physical_device, cmd_buffer->cs); } +/* 12.4 fixed-point */ +static unsigned radv_pack_float_12p4(float x) +{ + return x <= 0 ? 0 : + x >= 4096 ? 0xffff : x * 16; +} + static void si_emit_config(struct radv_physical_device *physical_device, struct radeon_winsys_cs *cs) @@ -486,6 +493,14 @@ si_emit_config(struct radv_physical_device *physical_device, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); } + + unsigned tmp = (unsigned)(1.0 * 8.0); + radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1); + radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); + radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1); + radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | + S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); + si_emit_compute(physical_device, cs); } |