diff options
| author | Dave Airlie <[email protected]> | 2017-09-11 07:44:19 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-09-11 23:55:15 +0100 |
| commit | f2d0f587ca898f7a7378e43668842194c723cb5b (patch) | |
| tree | 140cc116fa0d16351b46e57150c853d2e984bc44 /src/amd | |
| parent | ded1dbfd9616945ea235d186bc877b667d853d1e (diff) | |
radv: work out a base ia_multi_vgt_param.
This just reduces the calculations a bit further.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 7 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 15 |
3 files changed, 13 insertions, 10 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index b95b4f85c00..7d071533225 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2080,6 +2080,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline, } } + pipeline->graphics.base_ia_multi_vgt_param = + S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) | + /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ + S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) | + S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) | + S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9); + const VkPipelineVertexInputStateCreateInfo *vi_info = pCreateInfo->pVertexInputState; struct radv_vertex_elements_info *velems = &pipeline->vertex_elements; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index af3024f30ed..31991a314c8 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1086,6 +1086,7 @@ struct radv_pipeline { uint32_t pa_cl_vs_out_cntl; uint32_t vgt_shader_stages_en; uint32_t vtx_base_sgpr; + uint32_t base_ia_multi_vgt_param; bool wd_switch_on_eop; bool ia_switch_on_eoi; bool partial_vs_wave; diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 178855faac2..9f8d881d272 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -680,8 +680,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family; struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; - unsigned prim = cmd_buffer->state.pipeline->graphics.prim; - unsigned max_primgroup_in_wave = 2; + const unsigned max_primgroup_in_wave = 2; /* SWITCH_ON_EOP(0) is always preferable. */ bool wd_switch_on_eop = false; bool ia_switch_on_eop = false; @@ -728,6 +727,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, if (ia_switch_on_eoi && (family == CHIP_HAWAII || (chip_class == VI && + /* max primgroup in wave is always 2 - leave this for documentation */ (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2)))) partial_vs_wave = true; @@ -760,17 +760,12 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } } - return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | + return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param | + S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | - S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 1) | - S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) | - /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ - S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ? - max_primgroup_in_wave : 0) | - S_030960_EN_INST_OPT_BASIC(chip_class >= GFX9) | - S_030960_EN_INST_OPT_ADV(chip_class >= GFX9); + S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0); } |