diff options
| author | Samuel Pitoiset <[email protected]> | 2018-09-13 15:58:01 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-09-14 10:59:52 +0200 |
| commit | 40fb8c7fcabbbff2bb7fc8fe8f154e10baaaf138 (patch) | |
| tree | 31d6327568873481a1e11c93ba22a1a34b31adab /src/amd | |
| parent | a006c24237be3019292720dfff93214a3c037b86 (diff) | |
radv: fix setting the number of entries for GSVS on VI+
According to RadeonSI, it's unnecessary to multiply by
the stride. That field seems to always be 64.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index e3f63ce5f76..a6dbcd2a8b1 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3140,15 +3140,12 @@ ac_setup_rings(struct radv_shader_context *ctx) if (ctx->stage == MESA_SHADER_GEOMETRY) { LLVMValueRef tmp; uint32_t num_entries = 64; - LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false); LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false); ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false)); ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, ""); tmp = LLVMConstInt(ctx->ac.i32, num_entries, false); - if (ctx->options->chip_class >= VI) - tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, ""); ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), ""); tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, ""); tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, ""); |