diff options
| author | Dave Airlie <[email protected]> | 2018-01-24 12:53:26 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-01-25 06:47:28 +1000 |
| commit | 298554541da220ebdcd9aa9b9055ede2481d5817 (patch) | |
| tree | cff794b944778b29b60e5a8f6e4737f7edd396be /src/amd | |
| parent | 125c0529f3bb9607e2962acb95b2d4b97639b864 (diff) | |
radv: move spi_baryc_cntl to pipeline
We need to enable the pos float location 2 mode anytime we have
persample not just when forced by the frag shader.
This fixes:
dEQP-VK.pipeline.multisample.min_sample_shading*
Fixes: 58c97a079 (radv: enable location at sample when persample is forced.)
Reviewed-by: Samuel Pitoiset <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1143aa085f5..6d512c6070a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -990,7 +990,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, { struct radv_shader_variant *ps; uint64_t va; - unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); struct radv_blend_state *blend = &pipeline->graphics.blend; assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); @@ -1012,13 +1011,10 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR, ps->config.spi_ps_input_addr); - if (ps->info.info.ps.force_persample) - spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); - radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL, S_0286D8_NUM_INTERP(ps->info.fs.num_interp)); - radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); + radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT, pipeline->graphics.shader_z_format); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 21333b808ab..41a206a634e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -861,6 +861,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); + if (ps_iter_samples > 1) + pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); } const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = @@ -2449,6 +2451,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index), pStages); + pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra); radv_pipeline_init_raster_state(pipeline, pCreateInfo); radv_pipeline_init_multisample_state(pipeline, pCreateInfo); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 711ae719266..f650b9a360e 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1239,6 +1239,7 @@ struct radv_pipeline { struct radv_binning_state bin; uint32_t db_shader_control; uint32_t shader_z_format; + uint32_t spi_baryc_cntl; unsigned prim; unsigned gs_out; uint32_t vgt_gs_mode; |