diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-09-16 12:28:33 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2018-09-16 12:50:58 +0200 |
| commit | 0dd8189f159258ad8684036b0d696dbb58a268ca (patch) | |
| tree | 8a161bf55d48ec7076f16b8e66c104d2055dd44a /src/amd | |
| parent | d97c892584cd0641913de2635689c6b59c98816e (diff) | |
radv: Only allow 16 user SGPRs for compute on GFX9+.
Apparently for compute there are only 16 instead of the 32 for the
graphics path.
Fixes dEQP-VK.binding_model.descriptorset_random.sets16.noarray.ubolimitlow.sbolimitlow.imglimitlow.noiub.comp.0
CC: <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 968d96fc056..32d347ebd0f 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -689,7 +689,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx, if (ctx->shader_info->info.loads_push_constants) user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2; - uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16; + uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16; uint32_t remaining_sgprs = available_sgprs - user_sgpr_count; uint32_t num_desc_set = util_bitcount(ctx->shader_info->info.desc_set_used_mask); |