diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-01-05 01:36:26 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-02-01 01:09:05 +0100 |
| commit | 91074bb11bdaf58509d95736ac27aba48c1940e9 (patch) | |
| tree | 88c47fcdae34173cf3d205f9312a431ae25dd4eb /src/amd | |
| parent | 29577b21230a588b048b8e445fdf0dfabc695373 (diff) | |
radv/ac: Implement Float64 SSBO stores.
No f16 support as I'm not quite sure about alignment yet.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index be315851904..bdfad6a49a6 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2007,7 +2007,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx, nir_intrinsic_instr *instr) { const char *store_name; + LLVMValueRef src_data = get_src(ctx, instr->src[0]); LLVMTypeRef data_type = ctx->f32; + int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32; + int components_32bit = elem_size_mult * instr->num_components; unsigned writemask = nir_intrinsic_write_mask(instr); LLVMValueRef base_data, base_offset; LLVMValueRef params[6]; @@ -2020,10 +2023,10 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx, params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */ params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */ - if (instr->num_components > 1) - data_type = LLVMVectorType(ctx->f32, instr->num_components); + if (components_32bit > 1) + data_type = LLVMVectorType(ctx->f32, components_32bit); - base_data = to_float(ctx, get_src(ctx, instr->src[0])); + base_data = to_float(ctx, src_data); base_data = trim_vector(ctx, base_data, instr->num_components); base_data = LLVMBuildBitCast(ctx->builder, base_data, data_type, ""); @@ -2042,6 +2045,14 @@ static void visit_store_ssbo(struct nir_to_llvm_context *ctx, count = 2; } + start *= elem_size_mult; + count *= elem_size_mult; + + if (count > 4) { + writemask |= ((1u << (count - 4)) - 1u) << (start + 4); + count = 4; + } + if (count == 4) { store_name = "llvm.amdgcn.buffer.store.v4f32"; data = base_data; |