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authorMarek Olšák <[email protected]>2019-02-04 17:48:04 -0500
committerMarek Olšák <[email protected]>2019-05-16 13:07:00 -0400
commitb19884e08ed89325a732dea9d433e3039dfcb668 (patch)
tree1ce4719e2040a2a6ecd9d5847aa69d1028dee137 /src/amd
parenteda281e9772deee630275ddd7c23fbac841ecb38 (diff)
winsys/amdgpu: add a parallel compute IB coupled with a gfx IB
Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/common/ac_gpu_info.c7
-rw-r--r--src/amd/common/ac_gpu_info.h2
2 files changed, 9 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index db7f9e47ce1..2e8f943d204 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -397,6 +397,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->drm_minor >= 13;
info->has_2d_tiling = true;
info->has_read_registers_query = true;
+ info->has_scheduled_fence_dependency = info->drm_minor >= 28;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@@ -470,6 +471,10 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
else
info->use_display_dcc_with_retile_blit = true;
}
+
+ info->has_gds_ordered_append = info->chip_class >= GFX7 &&
+ info->drm_minor >= 29 &&
+ HAVE_LLVM >= 0x0800;
return true;
}
@@ -572,6 +577,8 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
+ printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
+ printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 11fb77eee87..ddbd09ff0bb 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -119,6 +119,8 @@ struct radeon_info {
bool has_sparse_vm_mappings;
bool has_2d_tiling;
bool has_read_registers_query;
+ bool has_gds_ordered_append;
+ bool has_scheduled_fence_dependency;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */