diff options
| author | Marek Olšák <[email protected]> | 2019-01-02 15:50:13 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-08-14 17:31:04 -0400 |
| commit | aafc95ceb6e9ebd62d456b95383ce7f05be0afd9 (patch) | |
| tree | 43a7f4c591ab632b45a58727fff5f635f17e1b1a /src/amd | |
| parent | a3d6024199723694980edbbca79c81ec215d8fcf (diff) | |
radeonsi: add support for Renoir
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/addrlib/src/amdgpu_asic_addr.h | 2 | ||||
| -rw-r--r-- | src/amd/addrlib/src/gfx9/gfx9addrlib.cpp | 5 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_llvm_util.c | 1 | ||||
| -rw-r--r-- | src/amd/common/amd_family.h | 1 |
5 files changed, 11 insertions, 1 deletions
diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h index 75c06796ad7..0358ab127b2 100644 --- a/src/amd/addrlib/src/amdgpu_asic_addr.h +++ b/src/amd/addrlib/src/amdgpu_asic_addr.h @@ -93,6 +93,7 @@ #define AMDGPU_RAVEN_RANGE 0x01, 0x81 #define AMDGPU_RAVEN2_RANGE 0x81, 0xFF +#define AMDGPU_RENOIR_RANGE 0x01, 0x91 #define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF @@ -141,6 +142,7 @@ #define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN) #define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2) +#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR) #define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS) diff --git a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp index 611c18fc1f0..cb0d3f054d7 100644 --- a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp +++ b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp @@ -1312,6 +1312,11 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily( m_settings.applyAliasFix = 1; } + if (ASICREV_IS_RENOIR(uChipRevision)) + { + m_settings.isRaven = 1; + } + m_settings.isDcn1 = m_settings.isRaven; m_settings.metaBaseAlignFix = 1; diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index b02a3e98113..9ec7359ed79 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -478,7 +478,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, if (info->drm_minor >= 31 && (info->family == CHIP_RAVEN || - info->family == CHIP_RAVEN2)) { + info->family == CHIP_RAVEN2 || + info->family == CHIP_RENOIR)) { if (info->num_render_backends == 1) info->use_display_dcc_unaligned = true; else diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index b43224b3b73..a201f2d1fc5 100644 --- a/src/amd/common/ac_llvm_util.c +++ b/src/amd/common/ac_llvm_util.c @@ -132,6 +132,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family) case CHIP_VEGA20: return "gfx906"; case CHIP_RAVEN2: + case CHIP_RENOIR: return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902"; case CHIP_ARCTURUS: return "gfx908"; diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index 1d6578c0ef7..2386eecb5d4 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -97,6 +97,7 @@ enum radeon_family { CHIP_VEGA20, CHIP_RAVEN, CHIP_RAVEN2, + CHIP_RENOIR, CHIP_ARCTURUS, CHIP_NAVI10, CHIP_NAVI12, |