diff options
author | Samuel Pitoiset <[email protected]> | 2019-05-22 15:38:47 +0200 |
---|---|---|
committer | Samuel Pitoiset <[email protected]> | 2019-05-27 13:52:34 +0200 |
commit | 9af15986b0d9ffcb69fcced33e59a61a8c54dfdd (patch) | |
tree | ade19653a3641da993e5b47b758f05c34f46495c /src/amd | |
parent | 13b38ca1e4341f5f16ae3ee9856552db12fda4cf (diff) |
radv: add radv_clear_htile() helper
This helper will be useful for clearing HTILE after some
depth/stencil resolves.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 7 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta.h | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 12 |
3 files changed, 16 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4f592bc7f68..43730f0568c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4389,19 +4389,14 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, { assert(range->baseMipLevel == 0); assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS); - unsigned layer_count = radv_get_layerCount(image, range); - uint64_t size = image->planes[0].surface.htile_slice_size * layer_count; VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT; - uint64_t offset = image->offset + image->htile_offset + - image->planes[0].surface.htile_slice_size * range->baseArrayLayer; struct radv_cmd_state *state = &cmd_buffer->state; VkClearDepthStencilValue value = {}; state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; - state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset, - size, clear_word); + state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word); state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index 5e0afd11a00..0bd75d6c207 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -211,6 +211,9 @@ uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t value); uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t value); +uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, + struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value); /* common nir builder helpers */ #include "nir/nir_builder.h" diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 40ecfe001d1..313e80d5cb7 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1344,6 +1344,18 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, image->planes[0].surface.dcc_size, value); } +uint32_t +radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value) +{ + unsigned layer_count = radv_get_layerCount(image, range); + uint64_t size = image->planes[0].surface.htile_slice_size * layer_count; + uint64_t offset = image->offset + image->htile_offset + + image->planes[0].surface.htile_slice_size * range->baseArrayLayer; + + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); +} + static void vi_get_fast_clear_parameters(VkFormat format, const VkClearColorValue *clear_value, uint32_t* reset_value, |