diff options
| author | Samuel Pitoiset <[email protected]> | 2020-01-21 09:13:46 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2020-01-23 14:40:48 +0100 |
| commit | 8d5203dad255b76501b74ac3cb5fcec977c7d21c (patch) | |
| tree | 929ef9b14e9c620c8ff6feab28b1045501a6e6c8 /src/amd | |
| parent | 4d9260171530f7fe9cc7a7ceffa5286355e546fc (diff) | |
aco: implement nir_op_f2i64/nir_op_f2u64 on GFX6
V_TRUNC_F64 and V_FLOOR_F64 needs to be lowered on GFX6.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index be65900aee2..1cbfed47b6a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2068,10 +2068,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } else if (instr->src[0].src.ssa->bit_size == 64) { Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u)); - Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src); + Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src); Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec); vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u)); - Temp floor = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul); + Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul); Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc); Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma); Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor); @@ -2137,10 +2137,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } else if (instr->src[0].src.ssa->bit_size == 64) { Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u)); - Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src); + Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src); Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec); vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u)); - Temp floor = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul); + Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul); Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc); Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma); Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor); |