diff options
| author | Dave Airlie <[email protected]> | 2017-07-24 17:09:47 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-07-24 17:27:55 +1000 |
| commit | 75392e76adf143070a5f208febd8da31b39b7676 (patch) | |
| tree | 1619bb2fdb2079271d1918804d6cc3f2b09eb84f /src/amd | |
| parent | 22b59b99cbee00689b68f1781ed0a10d74ffc49e (diff) | |
radv: fix non-0 based layer clears.
If the layer base was > 0, it wasn't getting passed as the start
instance or getting added in the shaders.
Fixes CTS dEQP-VK.api.image_clearing.core.clear_color_attachment.2d_r8_uint_multiple_layers
Fixes: 7e0382fb (radv: add support for layered clears (v2))
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index e9021915343..d007f97b30e 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -81,8 +81,10 @@ build_color_shaders(struct nir_shader **out_vs, vs_out_layer->data.location = VARYING_SLOT_LAYER; vs_out_layer->data.interpolation = INTERP_MODE_FLAT; nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0); + nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0); - nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1); + nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance); + nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1); *out_vs = vs_b.shader; *out_fs = fs_b.shader; @@ -398,7 +400,7 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect); - radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0); + radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer); radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false); } @@ -439,7 +441,10 @@ build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs vs_out_layer->data.location = VARYING_SLOT_LAYER; vs_out_layer->data.interpolation = INTERP_MODE_FLAT; nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0); - nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1); + nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0); + + nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance); + nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1); *out_vs = vs_b.shader; *out_fs = fs_b.shader; @@ -654,7 +659,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect); - radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0); + radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer); } static bool |