amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile

Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

4 files changed, 16 insertions, 14 deletions

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1ad9bfbb5fb..6b00eea8221 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1178,8 +1178,11 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 		hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 
-		hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-		hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
+		assert(in->flags.metaPipeUnaligned == 0);
+		assert(in->flags.metaRbUnaligned == 0);
+
+		hin.hTileFlags.pipeAligned = 1;
+		hin.hTileFlags.rbAligned = 1;
 		hin.depthFlags = in->flags;
 		hin.swizzleMode = in->swizzleMode;
 		hin.unalignedWidth = in->width;
@@ -1192,8 +1195,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		if (ret != ADDR_OK)
 			return ret;
 
-		surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
-		surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 		surf->htile_size = hout.htileBytes;
 		surf->htile_slice_size = hout.sliceSize;
 		surf->htile_alignment = hout.baseAlign;
@@ -1604,7 +1605,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	else
 		AddrSurfInfoIn.numSlices = config->info.array_size;
 
-	/* This is propagated to HTILE/DCC. */
+	/* This is propagated to DCC. It must be 0 for HTILE and CMASK. */
 	AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
 	AddrSurfInfoIn.flags.metaRbUnaligned = 0;
 
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 5a1381980f2..2f7b928f95f 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -150,7 +150,6 @@ struct gfx9_surf_layout {
     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 
     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
-    struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
     uint16_t                    surf_pitch; /* in blocks */
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 883d7d49efc..d4b78ef06df 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -6810,10 +6810,10 @@ radv_initialise_ds_surface(struct radv_device *device,
 				iview->image->htile_offset;
 			ds->db_htile_data_base = va >> 8;
 			ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
-				S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
+				S_028ABC_PIPE_ALIGNED(1);
 
 			if (device->physical_device->rad_info.chip_class == GFX9) {
-				ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
+				ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
 			}
 		}
 	} else {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 13877158924..12cf6fb6eb7 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -609,12 +609,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 			    C_00A018_META_PIPE_ALIGNED;
 
 		if (meta_va) {
-			struct gfx9_surf_meta_flags meta;
+			struct gfx9_surf_meta_flags meta = {
+				.rb_aligned = 1,
+				.pipe_aligned = 1,
+			};
 
 			if (image->dcc_offset)
 				meta = plane->surface.u.gfx9.dcc;
-			else
-				meta = plane->surface.u.gfx9.htile;
 
 			state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
 				    S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
@@ -637,12 +638,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 			    C_008F24_META_PIPE_ALIGNED &
 			    C_008F24_META_RB_ALIGNED;
 		if (meta_va) {
-			struct gfx9_surf_meta_flags meta;
+			struct gfx9_surf_meta_flags meta = {
+				.rb_aligned = 1,
+				.pipe_aligned = 1,
+			};
 
 			if (image->dcc_offset)
 				meta = plane->surface.u.gfx9.dcc;
-			else
-				meta = plane->surface.u.gfx9.htile;
 
 			state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
 				    S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |