aboutsummaryrefslogtreecommitdiffstats
path: root/src/amd
diff options
context:
space:
mode:
authorErico Nunes <[email protected]>2019-07-22 01:27:11 +0200
committerErico Nunes <[email protected]>2019-08-04 13:38:19 +0200
commit486b33558a5d5fe18fb87e98f75c34ef992428af (patch)
treeb820f414372b9662f77d1c1e36c6b74cf6dea19b /src/amd
parentfd29c4d6c561272ab34a71a308c36a0bb72b4816 (diff)
lima/ppir: simplify load uni/temp op lowering and scheduling
The load uniform/temporary operations output only to a pipeline register, which must be consumed by another op in the same instruction later. The current implementation delays the decision of who will consume this result to until the scheduling step. If the consumer node is not able to use the pipeline register, a mov node may have to be created, during the scheduler step. As part of the ppir scheduler simplification, and now that the ppir scheduler supports pipeline register dependencies, this can be simplified by always creating a single mov node outputting to a normal register that can be used directly by all consumers. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
Diffstat (limited to 'src/amd')
0 files changed, 0 insertions, 0 deletions