diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-02 12:16:54 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:16 +0200 |
| commit | 44a46c09deb96040ec25903e58e1ffc297b841c9 (patch) | |
| tree | b259e7030f8b3cd4388b67aac647c9b788dfa936 /src/amd | |
| parent | c08401f0353e941691a5f40945cbdd04030a94c7 (diff) | |
ac: add has_dcc_constant_encode to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 4 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 3 |
5 files changed, 6 insertions, 8 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index a3f1afe1f04..b6b37564c9f 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -450,6 +450,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_distributed_tess = info->chip_class >= GFX8 && info->max_se >= 2; + info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 || + info->family == CHIP_RENOIR || + info->chip_class >= GFX10; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 9ce1650c03c..10b578a1ef9 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -60,6 +60,7 @@ struct radeon_info { uint32_t tcc_cache_line_size; bool has_clear_state; bool has_distributed_tess; + bool has_dcc_constant_encode; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 83c6eb04e1e..ac9ec2e9b0d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2005,7 +2005,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) { bool disable_constant_encode = - cmd_buffer->device->physical_device->has_dcc_constant_encode; + cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode; enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; uint8_t watermark = chip_class >= GFX10 ? 6 : 4; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ad5c104f44f..a1927b9506c 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -386,10 +386,6 @@ radv_physical_device_init(struct radv_physical_device *device, (device->rad_info.chip_class >= GFX8 && device->rad_info.me_fw_feature >= 41); - device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 || - device->rad_info.family == CHIP_RENOIR || - device->rad_info.chip_class >= GFX10; - device->use_shader_ballot = device->rad_info.chip_class >= GFX8 && device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 287c2abfa3f..6c8d4b9c0a0 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -298,9 +298,6 @@ struct radv_physical_device { /* Whether to enable the AMD_shader_ballot extension */ bool use_shader_ballot; - /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */ - bool has_dcc_constant_encode; - /* Number of threads per wave. */ uint8_t ps_wave_size; uint8_t cs_wave_size; |