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authorSamuel Pitoiset <[email protected]>2019-05-30 10:26:43 +0200
committerSamuel Pitoiset <[email protected]>2019-06-07 13:11:14 +0200
commit05f5fa661f368b55a4105f7515f20aeae4025c52 (patch)
treee9a8ec34d237e313edf3d33575d55ca1e3a967f5 /src/amd
parente7677a697b9017cf44850f3ff3ac02e61dae2752 (diff)
radv: enable HTILE for images that might need variable sample locations
This is now supported. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-By: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
-rw-r--r--src/amd/vulkan/radv_image.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index afb426fc3c5..777af25445c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -76,13 +76,6 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
return false;
- /* TODO: Implement layout transitions with variable sample locations
- * before enabling HTILE for depth/stencil images created with this
- * flags because the depth decompress pass needs to know them.
- */
- if (pCreateInfo->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT)
- return false;
-
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
return false;