diff options
| author | Samuel Pitoiset <[email protected]> | 2018-06-22 19:16:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-06-26 18:23:16 +0200 |
| commit | fa42fa1a60debf26cdf86f40c0c805b0fc3b444f (patch) | |
| tree | 85282c42ab1e02cb43f2b6459bdb6ada50d7183a /src/amd | |
| parent | ab2643e4b06f63c93a57624003679903442634a8 (diff) | |
radv: emit PIPELINESTAT_{START,STOP} events for pipeline stats queries
Ported from RadeonSI.
This appears to fix some random fails with:
dEQP-VK.query_pool.statistics_query.*
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd')
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 4 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_query.c | 11 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 10 |
4 files changed, 29 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 62e1b9dba66..ad3465f594e 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2238,7 +2238,8 @@ radv_get_preamble_cs(struct radv_queue *queue, RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SMEM_L1 | RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_GLOBAL_L2); + RADV_CMD_FLAG_INV_GLOBAL_L2 | + RADV_CMD_FLAG_START_PIPELINE_STATS); } else if (i == 1) { si_cs_emit_cache_flush(cs, queue->device->physical_device->rad_info.chip_class, @@ -2248,7 +2249,8 @@ radv_get_preamble_cs(struct radv_queue *queue, RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SMEM_L1 | RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_GLOBAL_L2); + RADV_CMD_FLAG_INV_GLOBAL_L2 | + RADV_CMD_FLAG_START_PIPELINE_STATS); } if (!queue->device->ws->cs_finalize(cs)) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f001b836c8f..a202697e935 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -833,6 +833,9 @@ enum radv_cmd_flush_bits { RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10, RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11, RADV_CMD_FLAG_VGT_FLUSH = 1 << 12, + /* Pipeline query controls. */ + RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13, + RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14, RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META | @@ -966,6 +969,7 @@ struct radv_cmd_state { enum radv_cmd_flush_bits flush_bits; unsigned active_occlusion_queries; bool perfect_occlusion_queries_enabled; + unsigned active_pipeline_queries; float offset_scale; uint32_t trace_id; uint32_t last_ia_multi_vgt_param; diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index e1c91630ff4..384d75c210d 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1118,6 +1118,12 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer, case VK_QUERY_TYPE_PIPELINE_STATISTICS: radeon_check_space(cmd_buffer->device->ws, cs, 4); + ++cmd_buffer->state.active_pipeline_queries; + if (cmd_buffer->state.active_pipeline_queries == 1) { + cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS; + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS; + } + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, va); @@ -1157,6 +1163,11 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer, case VK_QUERY_TYPE_PIPELINE_STATISTICS: radeon_check_space(cmd_buffer->device->ws, cs, 16); + cmd_buffer->state.active_pipeline_queries--; + if (cmd_buffer->state.active_pipeline_queries == 0) { + cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS; + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS; + } va += pipelinestat_block_size; radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index e350bccae33..3491710ad86 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -937,6 +937,16 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, */ if (cp_coher_cntl) si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl); + + if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | + EVENT_INDEX(0)); + } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | + EVENT_INDEX(0)); + } } void |