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authorSamuel Pitoiset <[email protected]>2019-02-15 18:02:52 +0100
committerSamuel Pitoiset <[email protected]>2019-02-18 12:14:22 +0100
commit0d8f09629377da9cf48ab4315574d69fdef5369d (patch)
tree5c992a3a664e49746b6b90662cbb6df56d5d7e1a /src/amd/vulkan
parent2cf5433b99f989fa0ae1d2b108779e247145af85 (diff)
radv: write the alpha channel of MRT0 when alpha coverage is enabled
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597 Cc: 18.3 19.0 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_pipeline.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9745a1f2aa7..6b54da2e31b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -511,6 +511,13 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
cf = V_028714_SPI_SHADER_ZERO;
+
+ if (blend->need_src_alpha & (1 << i)) {
+ /* Write the alpha channel of MRT0 when alpha coverage is
+ * enabled because the depth attachment needs it.
+ */
+ col_format |= V_028714_SPI_SHADER_32_ABGR;
+ }
} else {
struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
bool blend_enable =
@@ -689,6 +696,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
if (vkms && vkms->alphaToCoverageEnable) {
blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
+ blend.need_src_alpha |= 0x1;
}
blend.cb_target_mask = 0;