diff options
author | Samuel Pitoiset <[email protected]> | 2019-06-20 09:17:34 +0200 |
---|---|---|
committer | Samuel Pitoiset <[email protected]> | 2019-06-20 11:03:53 +0200 |
commit | fa903ba799f16a74d74876baaf45daf808f71d59 (patch) | |
tree | 30a483e2a0aa339cfddfe5f105b77210f102d950 /src/amd/vulkan | |
parent | b92d87f7f0dc2dbd5b7a3d64a1a9a2863ab7262a (diff) |
radv: add radv_dcc_clear_level() helper
For clearing only one level.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r-- | src/amd/vulkan/radv_meta.h | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 30 |
2 files changed, 30 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h index 0cb31b9a7ec..5880064ff30 100644 --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -218,6 +218,9 @@ uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value); +uint32_t radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer, + const struct radv_image *image, + uint32_t level, uint32_t value); uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value); diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index c43ed6eeef1..dea0cae6d96 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1334,6 +1334,32 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, } uint32_t +radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer, + const struct radv_image *image, + uint32_t level, uint32_t value) +{ + uint64_t offset = image->offset + image->dcc_offset; + uint32_t size; + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* Mipmap levels aren't implemented. */ + assert(level == 0); + size = image->planes[0].surface.dcc_size; + } else { + const struct legacy_surf_level *surf_level = + &image->planes[0].surface.u.legacy.level[level]; + + /* If this is 0, fast clear isn't possible. */ + assert(surf_level->dcc_fast_clear_size); + + offset += surf_level->dcc_offset; + size = surf_level->dcc_fast_clear_size; + } + + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); +} + +uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) @@ -1341,9 +1367,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, /* Mark the image as being compressed. */ radv_update_dcc_metadata(cmd_buffer, image, range, true); - return radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->dcc_offset, - image->planes[0].surface.dcc_size, value); + return radv_dcc_clear_level(cmd_buffer, image, 0, value); } uint32_t |