diff options
| author | Dave Airlie <[email protected]> | 2016-11-24 00:18:21 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2016-11-29 22:48:03 +0000 |
| commit | f3a3fea973a145fe16f70866dcfc22c3c5322a91 (patch) | |
| tree | 0faefa4b5267b3f0d070885a68c446c432aa56df /src/amd/vulkan | |
| parent | 6a62026dd46a267eb861bcdf8a7db449745aa32e (diff) | |
radv: force persample shading when required.
We need to force persample shading when
a) shader uses sample_id
b) shader uses sample_position
c) shader uses sample qualifier.
Also since ps_iter_samples can now change independently of the
rasterizer samples we need to move setting the regs more often.
This fixes:
dEQP-VK.pipeline.multisample_interpolation.centroid_interpolate_at_consistency.*
dEQP-VK.pipeline.multisample_interpolation.centroid_qualifier_inside_primitive.137_191_1.*
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_distinct_values.*
dEQP-VK.pipeline.multisample_interpolation.sample_qualifier_distinct_values.128_128_1.*
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d1e4deb86c2..0eda0bceb49 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -288,6 +288,9 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]); + radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa); + radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); + if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples) return; @@ -295,9 +298,6 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config); - radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa); - radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); - radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples); uint32_t samples_offset; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7d7d0c672f9..23ed2d2df12 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1022,6 +1022,11 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, uint32_t mask = 0xffff; ms->num_samples = vkms->rasterizationSamples; + + if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) { + ps_iter_samples = vkms->rasterizationSamples; + } + ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1); ms->pa_sc_aa_config = 0; ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | |