diff options
| author | Samuel Pitoiset <[email protected]> | 2017-12-14 13:51:47 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-12-14 22:23:28 +0100 |
| commit | 88522e2bcd0e65ca619204f0eec96864323b94cb (patch) | |
| tree | dcd0fcf97122301e42c0ca0ff08e251e72fd1f1b /src/amd/vulkan | |
| parent | 45872a0a6d99d3f7704d9539f215eb0004c1e576 (diff) | |
radv: export SampleMask from pixel shaders at full rate
Use 16_ABGR instead of 32_ABGR if Z isn't written.
Ported from RadeonSI.
No CTS regressions on Polaris.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 0146d6935e0..1ada69d92f8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -46,6 +46,7 @@ #include "vk_format.h" #include "util/debug.h" #include "ac_exp_param.h" +#include "ac_shader_util.h" static void radv_pipeline_destroy(struct radv_device *device, @@ -2108,11 +2109,11 @@ radv_pipeline_init(struct radv_pipeline *pipeline, if (pipeline->device->physical_device->has_rbplus) pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); - pipeline->graphics.shader_z_format = - ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR : - ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR : - ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R : - V_028710_SPI_SHADER_ZERO; + unsigned shader_z_format = + ac_get_spi_shader_z_format(ps->info.fs.writes_z, + ps->info.fs.writes_stencil, + ps->info.fs.writes_sample_mask); + pipeline->graphics.shader_z_format = shader_z_format; calculate_vgt_gs_mode(pipeline); calculate_vs_outinfo(pipeline); |