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authorDave Airlie <[email protected]>2017-04-28 08:06:09 +0100
committerDave Airlie <[email protected]>2017-05-07 23:41:39 +0100
commit823e9ea8a1d8de6fb4378f53695367bc4a418e89 (patch)
tree2f5c5f12fdb6eb8d977e5550123838e1d19c5072 /src/amd/vulkan
parent2a04f5481df8ce6cb4c43382535ba9944cb3d723 (diff)
radv: drop resolve hack workarounds
This drops the resolve workarounds that change an image tiling mode behinds it's back, this is horrible and breaks the image_view->image relationship. Remove all this. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c40
-rw-r--r--src/amd/vulkan/radv_image.c62
-rw-r--r--src/amd/vulkan/radv_private.h3
3 files changed, 1 insertions, 104 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d5e559cd4e9..58746d3f9b8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -952,36 +952,6 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
ds->pa_su_poly_offset_db_fmt_cntl);
}
-/*
- * To hw resolve multisample images both src and dst need to have the same
- * micro tiling mode. However we don't always know in advance when creating
- * the images. This function gets called if we have a resolve attachment,
- * and tests if the attachment image has the same tiling mode, then it
- * checks if the generated framebuffer data has the same tiling mode, and
- * updates it if not.
- */
-static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
- struct radv_attachment_info *att,
- uint32_t micro_tile_mode)
-{
- struct radv_image *image = att->attachment->image;
- uint32_t tile_mode_index;
- if (image->info.samples <= 1)
- return;
-
- if (image->surface.micro_tile_mode != micro_tile_mode) {
- radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
- }
-
- if (att->cb.micro_tile_mode != micro_tile_mode) {
- tile_mode_index = image->surface.tiling_index[0];
-
- att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
- att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
- att->cb.micro_tile_mode = micro_tile_mode;
- }
-}
-
void
radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
@@ -1110,21 +1080,11 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
int i;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- int dst_resolve_micro_tile_mode = -1;
- if (subpass->has_resolve) {
- uint32_t a = subpass->resolve_attachments[0].attachment;
- const struct radv_image *image = framebuffer->attachments[a].attachment->image;
- dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
- }
for (i = 0; i < subpass->color_count; ++i) {
int idx = subpass->color_attachments[i].attachment;
struct radv_attachment_info *att = &framebuffer->attachments[idx];
- if (dst_resolve_micro_tile_mode != -1) {
- radv_set_optimal_micro_tile_mode(cmd_buffer->device,
- att, dst_resolve_micro_tile_mode);
- }
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 888561d59bc..e1e9d9c86b8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -770,68 +770,6 @@ radv_image_view_init(struct radv_image_view *iview,
blk_w, is_stencil, iview->descriptor);
}
-void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
- struct radv_image *image, uint32_t micro_tile_mode)
-{
- /* These magic numbers were copied from addrlib. It doesn't use any
- * definitions for them either. They are all 2D_TILED_THIN1 modes with
- * different bpp and micro tile mode.
- */
- if (device->physical_device->rad_info.chip_class >= CIK) {
- switch (micro_tile_mode) {
- case 0: /* displayable */
- image->surface.tiling_index[0] = 10;
- break;
- case 1: /* thin */
- image->surface.tiling_index[0] = 14;
- break;
- case 3: /* rotated */
- image->surface.tiling_index[0] = 28;
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- } else { /* SI */
- switch (micro_tile_mode) {
- case 0: /* displayable */
- switch (image->surface.bpe) {
- case 1:
- image->surface.tiling_index[0] = 10;
- break;
- case 2:
- image->surface.tiling_index[0] = 11;
- break;
- default: /* 4, 8 */
- image->surface.tiling_index[0] = 12;
- break;
- }
- break;
- case 1: /* thin */
- switch (image->surface.bpe) {
- case 1:
- image->surface.tiling_index[0] = 14;
- break;
- case 2:
- image->surface.tiling_index[0] = 15;
- break;
- case 4:
- image->surface.tiling_index[0] = 16;
- break;
- default: /* 8, 16 */
- image->surface.tiling_index[0] = 17;
- break;
- }
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- }
-
- image->surface.micro_tile_mode = micro_tile_mode;
-}
-
bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout)
{
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 97bf6613832..1e023560945 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1249,8 +1249,7 @@ void radv_image_view_init(struct radv_image_view *view,
const VkImageViewCreateInfo* pCreateInfo,
struct radv_cmd_buffer *cmd_buffer,
VkImageUsageFlags usage_mask);
-void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
- struct radv_image *image, uint32_t micro_tile_mode);
+
struct radv_buffer_view {
struct radeon_winsys_bo *bo;
VkFormat vk_format;