diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-04-30 17:49:15 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-05-02 00:54:18 +0200 |
| commit | 568aec29d9eb57c05668f061677d5e9bc3b4de97 (patch) | |
| tree | 7698c269caab3e45d252933917f2a153bffc9bb3 /src/amd/vulkan | |
| parent | 14ae0bfa5400f2a325b93040a8e7734332c7469f (diff) | |
radv: Add top of pipe timestamp queries.
Does not fix brokenness with the ready bit.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_query.c | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 7e0fd1d073f..0991c267000 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1196,21 +1196,35 @@ void radv_CmdWriteTimestamp( MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12); - if (mec) { - radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); - radeon_emit(cs, 3 << 29); - radeon_emit(cs, query_va); - radeon_emit(cs, query_va >> 32); + switch(pipelineStage) { + case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT: + radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM | + COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) | + COPY_DATA_DST_SEL(V_370_MEM_ASYNC)); radeon_emit(cs, 0); radeon_emit(cs, 0); - } else { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); radeon_emit(cs, query_va); - radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF)); - radeon_emit(cs, 0); - radeon_emit(cs, 0); + radeon_emit(cs, query_va >> 32); + break; + default: + if (mec) { + radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); + radeon_emit(cs, 3 << 29); + radeon_emit(cs, query_va); + radeon_emit(cs, query_va >> 32); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } else { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); + radeon_emit(cs, query_va); + radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF)); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } + break; } radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); |