diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-07-07 15:56:57 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-07-08 16:11:29 +0200 |
| commit | 1aba0e7f5841087058d57ea5286dbc30d8869982 (patch) | |
| tree | 19d0dff9262943f6ae6844ce51a9cb94c62c1ca0 /src/amd/vulkan | |
| parent | 4db72852a16fc4a2a559255f9965e1d02e4f2b9c (diff) | |
radv: Add compute htile clear for combined depth+stencil surfaces.
Figured out the clear value when we have a combined depth stencil
surface.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index bd979973e71..7f3cfdccc86 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -708,17 +708,15 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer, if (clear_rect->layerCount != iview->image->info.array_size) goto fail; - /* Don't do stencil clears till we have figured out if the clear words are - * correct. */ - if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) + if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) goto fail; - if (clear_value.depth == 1.0) - clear_word = 0xfffffff0; - else if (clear_value.depth == 0.0) - clear_word = 0; - else - goto fail; + if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) { + if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) + goto fail; + clear_word = clear_value.depth ? 0xfffc0000 : 0; + } else + clear_word = clear_value.depth ? 0xfffffff0 : 0; if (pre_flush) { cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB | |