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authorSamuel Pitoiset <[email protected]>2018-03-29 10:49:33 +0200
committerSamuel Pitoiset <[email protected]>2018-04-04 13:32:00 +0200
commita8818d1af2c5810ea9236f9962fd887b52418f9f (patch)
tree9ad86876e492a9f94ffb90d6d61ca656bcb09790 /src/amd/vulkan
parentac456d0d1b45a7df38dc7016d51591496500eeed (diff)
radv: scan which color blend attachments are enabled
With cb_target_enabled_4bit in order to have four bits per CB. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_pipeline.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 026bf83cc55..bf73214bbb7 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -55,6 +55,7 @@ struct radv_blend_state {
uint32_t cb_color_control;
uint32_t cb_target_mask;
+ uint32_t cb_target_enabled_4bit;
uint32_t sx_mrt_blend_opt[8];
uint32_t cb_blend_control[8];
@@ -578,6 +579,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
continue;
blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
+ blend.cb_target_enabled_4bit |= 0xf << (4 * i);
if (!att->blendEnable) {
blend.cb_blend_control[i] = blend_cntl;
continue;