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authorSamuel Pitoiset <[email protected]>2019-08-02 12:21:04 +0200
committerSamuel Pitoiset <[email protected]>2019-08-27 08:04:19 +0200
commit63c0b89b8f49f2b8c029d206fd18620a19d33e1d (patch)
treeb34189a509396797b2e34fd22c4e4665e14c1d8a /src/amd/vulkan
parent44a46c09deb96040ec25903e58e1ffc297b841c9 (diff)
ac: add has_rbplus to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_device.c1
-rw-r--r--src/amd/vulkan/radv_pipeline.c6
-rw-r--r--src/amd/vulkan/radv_private.h1
3 files changed, 3 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a1927b9506c..3726ad0ec78 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -356,7 +356,6 @@ radv_physical_device_init(struct radv_physical_device *device,
if (device->rad_info.family == CHIP_STONEY ||
device->rad_info.chip_class >= GFX9) {
- device->has_rbplus = true;
device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
device->rad_info.family == CHIP_VEGA12 ||
device->rad_info.family == CHIP_RAVEN ||
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 584dddb48df..97ab503bef3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
}
- if (pipeline->device->physical_device->has_rbplus) {
+ if (pipeline->device->physical_device->rad_info.has_rbplus) {
/* Disable RB+ blend optimizations for dual source blending. */
if (blend.mrt0_is_dual_src) {
for (i = 0; i < 8; i++) {
@@ -3329,7 +3329,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
- if (pipeline->device->physical_device->has_rbplus) {
+ if (pipeline->device->physical_device->rad_info.has_rbplus) {
radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
@@ -4054,7 +4054,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
else
z_order = V_02880C_LATE_Z;
- bool disable_rbplus = device->physical_device->has_rbplus &&
+ bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
!device->physical_device->rbplus_allowed;
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 6c8d4b9c0a0..c507945e9eb 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,7 +280,6 @@ struct radv_physical_device {
int master_fd;
struct wsi_device wsi_device;
- bool has_rbplus; /* if RB+ register exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool cpdma_prefetch_writes_memory;
bool has_scissor_bug;