diff options
| author | Dave Airlie <[email protected]> | 2016-11-28 00:57:30 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2016-12-07 23:25:45 +0000 |
| commit | 221ab77956d20a999da34c8bd2ace4bc06f4ee42 (patch) | |
| tree | 703a3c4155f4b918c6c05edf5ba5396f5f836755 /src/amd/vulkan | |
| parent | 11208f0049431a08328692874988503cd7742ede (diff) | |
radv: refactor out the constant setting user sgpr code.
This just refactors out some common code to make future changes
easier to understand.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 54a9158d53c..8a22ec40ad0 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -943,6 +943,17 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, } static void +emit_constants_set_userdata(struct radv_cmd_buffer *cmd_buffer, + uint64_t va, + uint32_t base_reg) +{ + radeon_set_sh_reg_seq(cmd_buffer->cs, + base_reg + 4 * AC_USERDATA_PUSH_CONST_DYN, 2); + radeon_emit(cmd_buffer->cs, va); + radeon_emit(cmd_buffer->cs, va >> 32); +} + +static void radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline, VkShaderStageFlags stages) @@ -967,26 +978,14 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo); va += offset; - if (stages & VK_SHADER_STAGE_VERTEX_BIT) { - radeon_set_sh_reg_seq(cmd_buffer->cs, - R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_PUSH_CONST_DYN * 4, 2); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); - } + if (stages & VK_SHADER_STAGE_VERTEX_BIT) + emit_constants_set_userdata(cmd_buffer, va, R_00B130_SPI_SHADER_USER_DATA_VS_0); - if (stages & VK_SHADER_STAGE_FRAGMENT_BIT) { - radeon_set_sh_reg_seq(cmd_buffer->cs, - R_00B030_SPI_SHADER_USER_DATA_PS_0 + AC_USERDATA_PUSH_CONST_DYN * 4, 2); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); - } + if (stages & VK_SHADER_STAGE_FRAGMENT_BIT) + emit_constants_set_userdata(cmd_buffer, va, R_00B030_SPI_SHADER_USER_DATA_PS_0); - if (stages & VK_SHADER_STAGE_COMPUTE_BIT) { - radeon_set_sh_reg_seq(cmd_buffer->cs, - R_00B900_COMPUTE_USER_DATA_0 + AC_USERDATA_PUSH_CONST_DYN * 4, 2); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); - } + if (stages & VK_SHADER_STAGE_COMPUTE_BIT) + emit_constants_set_userdata(cmd_buffer, va, R_00B900_COMPUTE_USER_DATA_0); cmd_buffer->push_constant_stages &= ~stages; } |