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authorDave Airlie <[email protected]>2018-01-25 09:29:55 +1000
committerDave Airlie <[email protected]>2018-01-26 06:55:09 +1000
commitf4c534ef68a479055190f8ec8d551be0f56ef361 (patch)
tree50cfad10e66d10dd703b2db2b1cca3315be0935f /src/amd/vulkan
parent6ac5e851f1a0b83d84156bc79983fd9527d4c296 (diff)
radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)
This seems to be broken, at least the cts tests fail. This fixes: dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_4 dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_8 2 samples seems to pass fine, amdvlk doesn't appear to enable TC for possibly some other reasons here. This is most likely a hack. v1.1: add a bit of explaination text. (Samuel) Fixes: ad3d98da9 (radv: enable tc compatible htile for d32s8 also.) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_image.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 54b2b5247d2..7babcb4e50c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -116,7 +116,8 @@ radv_init_surface(struct radv_device *device,
pCreateInfo->mipLevels <= 1 &&
device->physical_device->rad_info.chip_class >= VI &&
((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
- pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
+ /* for some reason TC compat with 4/8 samples breaks some cts tests - disable for now */
+ (pCreateInfo->samples < 4 && pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)) ||
(device->physical_device->rad_info.chip_class >= GFX9 &&
pCreateInfo->format == VK_FORMAT_D16_UNORM)))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;