diff options
| author | Samuel Pitoiset <[email protected]> | 2018-02-28 20:28:53 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-03-01 09:53:40 +0100 |
| commit | c27f5419f6f6aa6d51b44a99b6738fba70873604 (patch) | |
| tree | a9496986edbbbd38708ed3b51b88b6481911b9db /src/amd/vulkan | |
| parent | 2fe07933bd5385f731b490ba22ee2086bfccfe63 (diff) | |
radv: only emit cache flushes when the pool size is large enough
This is an optimization which reduces the number of flushes for
small pool buffers.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_meta_buffer.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_query.c | 14 |
3 files changed, 15 insertions, 11 deletions
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index e6ad235e93b..2e1ba2c7b22 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -4,12 +4,6 @@ #include "sid.h" #include "radv_cs.h" -/* - * This is the point we switch from using CP to compute shader - * for certain buffer operations. - */ -#define RADV_BUFFER_OPS_CS_THRESHOLD 4096 - static nir_shader * build_buffer_fill_shader(struct radv_device *dev) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 752b6a75922..0f8ddb2e106 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -95,6 +95,12 @@ typedef uint32_t xcb_window_t; #define NUM_DEPTH_CLEAR_PIPELINES 3 +/* + * This is the point we switch from using CP to compute shader + * for certain buffer operations. + */ +#define RADV_BUFFER_OPS_CS_THRESHOLD 4096 + enum radv_mem_heap { RADV_MEM_HEAP_VRAM, RADV_MEM_HEAP_VRAM_CPU_ACCESS, diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index ff2782bae89..9fee4d2b491 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1092,11 +1092,15 @@ void radv_CmdBeginQuery( radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8); if (cmd_buffer->pending_reset_query) { - /* Make sure to flush caches if the query pool has been - * previously resetted using the compute shader path. - */ - si_emit_cache_flush(cmd_buffer); - cmd_buffer->pending_reset_query = false; + if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) { + /* Only need to flush caches if the query pool size is + * large enough to be resetted using the compute shader + * path. Small pools don't need any cache flushes + * because we use a CP dma clear. + */ + si_emit_cache_flush(cmd_buffer); + cmd_buffer->pending_reset_query = false; + } } switch (pool->type) { |